IC Substrate Expansion Analysis Testing: Methods, Standards, and Reliability Assessment

IC substrate expansion analysis testing measures the coefficient of thermal expansion (CTE), glass transition temperature (Tg), and warpage behavior of package substrates to ensure dimensional stability and long-term reliability in advanced semiconductor packaging. Using techniques such as TMA, DMA, DSC, and shadow moiré interferometry, this testing evaluates how BT resin, ABF build-up films, and multilayer substrates deform under thermal loads. The results guide material selection, CTE matching between die, substrate, and PCB, and warpage control during reflow assembly.

Technical Overview

IC substrates, also known as package substrates, serve as the critical interposer between the silicon die and the printed circuit board, providing electrical routing, power distribution, and mechanical support. Because these substrates operate in an environment where multiple materials with vastly different thermal expansion behaviors are joined together—silicon at approximately 2.6 ppm/°C, copper at approximately 17 ppm/°C, and organic substrate materials typically ranging from 10 to 20 ppm/°C in-plane—expansion analysis is fundamental to package reliability.

When a package undergoes thermal cycling during manufacturing, reflow, or field operation, coefficient of thermal expansion (CTE) mismatch generates thermomechanical stresses at every material interface. These stresses manifest as solder joint fatigue, copper via barrel cracking, interfacial delamination, and substrate warpage. Expansion analysis testing quantifies the dimensional response of substrate materials as a function of temperature, providing the data required to predict and prevent these failure modes.

• In-plane expansion governs the stress transferred to solder bumps and die attach layers, directly affecting joint reliability.
• Z-axis (through-thickness) expansion determines the strain imposed on plated through-holes and laser-drilled microvias, which is the dominant driver of interconnect cracking.
• Warpage, the out-of-plane deformation of the assembled substrate, determines whether a package can be successfully mounted during SMT assembly.

Comprehensive expansion analysis therefore combines coefficient measurement, glass transition characterization, and full-field deformation mapping to give packaging engineers a complete thermomechanical profile of the substrate.

Testing Samples

Core Materials and Copper-Clad Laminates

Core substrates form the structural backbone of the package and are tested first in their raw laminate form. Common samples include bismaleimide triazine (BT) resin cores used in memory and RF packages, FR-4 and modified epoxy glass cores, low-CTE glass-fabric-reinforced laminates, and emerging glass-core substrates for advanced fan-out and 2.5D applications. Copper-clad laminate (CCL) coupons may be tested with copper either intact, etched away, or in both conditions to separate the contributions of resin system and metal foil.

Build-up Films and Prepregs

Ajinomoto Build-up Film (ABF) and other dielectric build-up materials define the fine-pitch rewiring layers of flip-chip substrates. Because these films are tested after lamination and cure on the core, coupons are prepared using production-representative press cycles to capture the actual crosslinked state. Prepreg samples used in multilayer lamination are similarly cured before measurement.

Finished Multilayer Substrates and Coupons

Fabricated substrates with complete build-up layers, finished copper metallization, solder mask, and surface finishes (ENIG, ENEPIG, EPIG) are tested to evaluate the effective composite expansion behavior. Test coupons incorporating the full layer stack, including via arrays, provide realistic data for reliability modeling.

Assembled Packages

Populated units with attached die, underfill, and mold compound are evaluated primarily for warpage behavior rather than material coefficient, since the assembled structure represents the final thermomechanical system.

Testing Items

Expansion analysis covers a defined set of measurable parameters, each tied to a specific reliability concern:

• Alpha 1 CTE (below Tg): the in-plane or Z-axis expansion coefficient in the glassy region, typically measured from 50 °C to the onset of transition; this value dominates field-use reliability.
• Alpha 2 CTE (above Tg): the expansion coefficient in the rubbery region, which is typically two to four times higher and governs behavior during reflow excursions.
• Glass transition temperature (Tg): measured by TMA (onset of expansion change), DMA (peak of tan delta), or DSC (step change in heat capacity), with each method yielding systematically different values that must not be interchanged.
• Percent total expansion (PTE): the cumulative dimensional change across a defined span such as 50–260 °C, a key acceptance metric for Z-axis expansion and via reliability.
• Modulus versus temperature: storage modulus retention above Tg indicates structural integrity during reflow.
• Dimensional stability: permanent shrinkage or growth after thermal excursions, measured as post-heat-treatment dimensional change.
• Warpage (hot and cold): out-of-plane displacement of the substrate or package measured at room temperature and across a reflow profile.
• Moisture-dependent expansion: hygroscopic swelling and its interaction with thermal expansion in moisture-sensitive dielectric materials.

Testing Methods

Thermomechanical Analysis (TMA)

TMA is the primary method for direct expansion coefficient measurement. A specimen, typically 3 to 6 mm square and 0.1 to 1.5 mm thick, is placed under a low-force expansion probe and heated at a controlled rate, commonly 5 °C/min, under nitrogen. The instrument records dimensional change versus temperature, from which alpha 1 and alpha 2 are extracted by linear regression and Tg is determined by the extrapolated onset of the slope change. Testing follows ASTM E831 and IPC-TM-650 method 2.4.24 series procedures. Z-axis CTE requires specimen thickness of at least several hundred microns or stacked laminates to achieve acceptable measurement resolution.

Dynamic Mechanical Analysis (DMA)

DMA applies oscillatory load to a coupon in three-point bending, tension, or dual cantilever mode while sweeping temperature. It yields storage modulus, loss modulus, and tan delta, providing the Tg by mechanical relaxation and the stiffness retention that TMA cannot capture. DMA data are essential for finite element warpage simulation of substrates during reflow. Relevant standards include ASTM D4065 and ASTM E1640.

Differential Scanning Calorimetry (DSC)

DSC measures Tg as the step change in heat capacity and verifies degree of cure, which strongly influences both expansion behavior and moisture uptake. ASTM E1356 defines the midpoint determination procedure. DSC Tg values typically run lower than TMA Tg and significantly lower than DMA tan delta peak values, so reported Tg must always reference its measurement method.

Shadow Moiré Warpage Measurement

Full-field out-of-plane displacement of substrates and assembled packages is measured using shadow moiré or projection moiré interferometry per JEDEC standard JESD22-B112. The sample is heated inside an oven following a simulated reflow profile while a reference grating casts fringe patterns across the surface. Fringe analysis resolves warpage contour maps at each temperature step, capturing both maximum deflection and deformation mode (concave versus convex). This method directly validates SMT assembly processability.

Sample Conditioning and Pretreatment

Because organic substrates absorb ambient moisture that suppresses Tg and inflates apparent expansion, specimens are baked prior to TMA, DMA, and DSC testing, typically at 105 to 125 °C for two to four hours, then tested promptly. Assembled packages requiring moisture sensitivity evaluation undergo preconditioning per JEDEC J-STD-020 before warpage measurement so that results reflect worst-case absorbed-moisture conditions.

Supplementary Techniques

Digital image correlation (DIC) provides full-field in-plane strain mapping on flat coupons, while cyclic thermal chamber exposure with intermediate TMA re-measurement assesses irreversible expansion shift caused by post-cure and moisture history over the product lifetime.

Applications

Expansion analysis testing supports every stage of the IC substrate and package development lifecycle:

• Material qualification: incoming inspection and supplier qualification of BT cores, ABF build-up films, prepregs, and glass cores against CTE, Tg, and PTE specifications defined in IPC-4101 slash sheets and customer-specific procurement documents.
• Package design and CTE matching: selecting low-CTE cores and build-up stacks so that the effective substrate expansion approaches that of silicon, minimizing bump stress in flip-chip designs and enabling large-body BGA and LGA packages.
• Via and interconnect reliability: qualifying Z-axis expansion to prevent copper barrel cracking, microvia pull-away, and capture-pad separation during thermal cycling.
• Warpage control for SMT: validating that coplanarity limits are maintained at reflow peak temperature so packages seat properly on board, avoiding open joints and head-on-pillow defects.
• Advanced packaging: supporting 2.5D/3D architectures with silicon interposers and RDL fan-out structures where extremely tight CTE windows are required between die, interposer, substrate, and mold compound.
• Failure analysis: comparing expansion behavior of failed units against known-good material to identify under-cure, moisture degradation, or material substitution as root causes of delamination and cracking.
• High-reliability markets: automotive, aerospace, 5G infrastructure, and AI accelerator hardware, where AEC-Q and customer standards impose strict thermal cycling survival requirements.

FAQ

Why is CTE mismatch such a critical issue for IC substrates? The silicon die expands at roughly 2.6 ppm/°C while typical organic substrates expand at 10–20 ppm/°C in-plane. Every temperature excursion therefore shears the solder bumps and die interface. Excessive mismatch accelerates joint fatigue, underfill delamination, and low-k dielectric cracking in the chip itself.

What are typical CTE targets for package substrates? In-plane CTE is usually specified between 10 and 17 ppm/°C depending on the die size and application, while Z-axis expansion is controlled by limiting percent total expansion, commonly below 3.5–4.0 percent over 50–260 °C for build-up dielectrics used in flip-chip substrates.

What sample dimensions are required for TMA testing? Z-axis measurements use specimens 3 to 6 mm square with sufficient thickness for resolution, ideally 0.3 mm or greater or a stack of laminated plies. X-Y measurements require a flat coupon with straight, parallel edges cut accurately along the material axes.

Why do TMA, DMA, and DSC report different Tg values for the same material? The three techniques detect different physical phenomena: heat capacity step (DSC), dimensional slope change (TMA), and mechanical relaxation peak (DMA). Values increase in the order DSC, TMA, DMA tan delta peak, often by 10 to 25 °C. Specifications must always cite the measurement method.

How does absorbed moisture affect expansion test results? Moisture plasticizes epoxy and ABF dielectrics, lowering apparent Tg, increasing expansion rates, and adding hygroscopic swelling. Proper pre-test baking is mandatory, and separate hygroscopic swelling measurements are recommended for moisture-sensitive designs.

Which standards govern IC substrate expansion testing? Core references include ASTM E831 (TMA CTE), ASTM E1356 (DSC Tg), ASTM D4065 and E1640 (DMA), IPC-TM-650 method 2.4.24 series for laminate expansion and Tg, IPC-4101 for material specification limits, JEDEC JESD22-B112 for warpage, and JEDEC J-STD-020 for moisture preconditioning.